1. Field
This disclosure relates generally to semiconductor device design verification, and more specifically, to a method and system for checking generated device mask layers for agreement with design schematics.
2. Related Art
Semiconductor device design and fabrication flow typically involves a sequence of steps that progress from input of a device schematic toward generation of layer masks used in manufacturing the physical device. During the course of this flow, rules and verifications are applied.
An early step in device and fabrication flow involves generation of a physical layout for the device. Verification of the physical layout is typically performed by comparing attributes of the physical layout (e.g., device characteristics and connectivity) with those of the initial as-designed schematic for the device. In addition, the physical layout is subject to design rules checks (DRC) for physical characteristics such as, for example, size and spacing. Once this layout-to-schematic (LVS) verification has been performed, the design tapes out and is passed to post-tapeout operations. Post-tapeout operations provide for generation of integrated circuit (IC) mask layers from the taped-out CAD layers. Certain of these layers may not included in the CAD layers (e.g., p-well layers (PW), n-channel lightly-doped drain layers (NLDD), and the like) and are typically generated by application of computational mask operations (e.g., Boolean or CAD-to-Mask operations). In addition, other post-tapeout operations such as optical proximity correction (OPC) modify the generated IC mask description. Ultimately, in a typical design and fabrication flow, the IC masks are visually inspected for issues that may have arisen during the course of mask layer generation.
The translation of the design description to IC mask shapes through the use of the computational methods and other foundry-level operations can result in IC mask shape and layer interactions that may be problematic in the ultimate device, but which would not be caught by design rules checking and LVS, nor which are easily visually detected. It is therefore desirable to provide a design flow that includes a mechanism for detecting issues that arise during the course of mask generation.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.